UCIe Consortium Incorporates, Adds NVIDIA and Alibaba As Members

Among the groups with a presence at this year’s Flash Memory Summit is the UCIe Consortium, the recently formed group responsible for the Universal Chiplet Interconnect Express (UCIe) standard. First unveiled back in March, the UCIe Consortium is looking to establish a universal standard for connecting chiplets in future chip designs, allowing chip builders to mix-and-match chiplets from different companies. At the time of the March announcement, the group was looking for additional members as it prepared to formally incorporate, and for FMS they’re offering a brief update on their progress.

First off, the group has now become officially incorporated. And while this is largely a matter of paperwork for the group, it’s none the less an important step as it properly establishes them as a formal consortium. Among other things, this has allowed the group to launch their work groups for developing future versions of the standard, as well as to offer initial intellectual property rights (IPR) protections for members.

More significant, however, is the makeup of the incorporated UCIe board. While UCIe was initially formed with 10 members – a veritable who’s who of many of the big players in the chip industry – there were a couple of notable absences. The incorporated board, in turn, has picked up two more members who have bowed to the peer (to peer) pressure: NVIDIA and Alibaba.

NVIDIA for its part has already previously announced that it would support UCIe in future products (even if it’s still pushing customers to use NVLink), so their addition to the board is not unexpected. Still, it brings on board what’s essentially the final major chip vendor, firmly establishing support for UCIe across all of the ecosystem’s big players. Meanwhile, like Meta and Google Cloud, Alibaba represents another hyperscaler joining the group, who will presumably be taking full advantage of UCIe in developing chips for their datacenters and cloud computing services.

Overall, according to the Consortium the group is now up to 60 members total. And they are still looking to add more through events like FMS as they roll on towards getting UCIe 1.0 implemented in production chiplets.

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SK hynix Announces 238 Layer NAND – Mass Production To Start In H1’2023

As the 2022 Flash Memory Summit continues, SK hynix is the latest vendor to announce their next generation of NAND flash memory at the show. Showcasing for the first time the company’s forthcoming 238 layer TLC NAND, which promises both improved density/capacity and improved bandwidth. At 238 layers, SK hynix has, at least for the moment, secured bragging rights for the greatest number of layers in a TLC NAND die – though with mass production not set to begin until 2023, it’s going to be a while until the company’s newest NAND shows up in retail products.

Following closely on the heels of Micron’s 232L TLC NAND announcement last week, SK hynix is upping the ante ever so slightly with a 238 layer design. Though the difference in layer counts is largely inconsequential when you’re talking about NAND dies with 200+ layers to begin with, in the highly competitive flash memory industry it gives SK hynix bragging rights on layer counts, breaking the previous stalemate between them, Samsung, and Micron at 176L.

From a technical perspective, SK hynix’s 238L NAND further builds upon the basic design of their 176L NAND. So we’re once again looking at a string stacked design, with SH hynix using a pair of 119 layer decks, up from 88 layers in the previous generation. This makes SK hynix the third flash memory vendor to master building decks over 100 layers tall, and is what’s enabling them to produce a 238L NAND design that holds the line at two decks.

SK hynix’s NAND decks continue to be built with their charge-trap, CMOS under Array (CuA) architecture, which sees the bulk of the NAND’s logic placed under the NAND memory cells. According to the company, their initial 512Gbit TLC part has a die size of 35.58mm2, which works out to a density of roughly 14.39 Gbit/mm2. That’s a 35% improvement in density over their previous-generation 176L TLC NAND die at equivalent capacities. Notably, this does mean that SK hynix will be ever so slightly trailing Micron’s 232L NAND despite their total layer count advantage, as Micron claims they’ve hit a density of 14.6 Gbit/mm2 on their 1Tbit dies.

SK hynix 3D TLC NAND Flash Memory
 
238L
176L
Layers
238
176
Decks
2 (x119)
2 (x88)
Die Capacity
512 Gbit
512 Gbit
Die Size (mm2)
35.58mm2
~47.4mm2
Density (Gbit/mm2)
~14.39
10.8
I/O Speed
2.4 MT/s
(ONFi 5.0)
1.6 MT/s
(ONFI 4.2)
CuA / PuC
Yes
Yes

Speaking of 1Tbit, unlike Micron, SK hynix is not using the density improvements to build higher capacity dies – at least, not yet. While the company has announced that they will be building 1Tbit dies next year using their 238L process, for now they’re holding at 512Gbit, the same capacity as their previous generation. So all other factors held equal, we shouldn’t expect the first wave drives built using 238L NAND to have any greater capacity than the current generation. But, if nothing else, at least SK hynix’s initial 238L dies are quite small – though whether that translates at all to smaller packages remains to be seen.

Besides density improvements, SK hynix has also improved the performance and power consumption of their NAND. Like the other NAND vendors, SK hynix is using this upcoming generation of NAND to introduce ONFi 5.0 support. ONFi 5.0 is notable for not only increasing the top transfer rate to 2400MT/second – a 50% improvement over ONFi 4.2 – but it also introduces a new NV-LPDDR4 signaling method. As it’s based on LPDDR signaling (unlike the DDR3-derrived mode in ONFi 4.x), NV-LPDDR4 offers tangible reductions in the amount of power consumed by NAND signaling. SK hynix isn’t breaking their power consumption figures out to this level of detail, but for overall power consumption, they’re touting a 21% reduction in energy consumed for read operations. Presumably this is per bit, so it will be counterbalanced by the 50% improvement in bandwidth.

This week’s announcement comes as SK hynix has begun shipping samples of the 238L NAND to their customers. As previously mentioned, the company is not planning on kicking off mass production until H1’2023, so it will be some time before we see the new NAND show up in retail products. According to SK hynix, their plan is to start with shipping NAND for consumer SSDs, followed by smartphones and high-capacity server SSDs. That, in turn, will be followed up with the introduction of 1Tbit 238L NAND later in 2023.

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Solidigm Announces P41 Plus SSD: Taking Another Shot at QLC With Cache Tiering

Although Intel is no longer directly in the SSD market these days, their SSD team and related technologies continue to live on under the SK hynix umbrella as Solidigm. Since their initial formation at the very end of 2021, Solidigm has been in the process of reestablishing their footing, continuing to sell and support Intel’s previous SSD portfolio while continuing development of their next generation of SSDs. On the enterprise side of matters this recently culminated in the launch of their new D7 SSDs. Meanwhile on the consumer side of matters, today at Flash Memory Summit the company is announcing their first post-Intel consumer SSD, the Solidigm P41 Plus

The P41 Plus is, at a high level, the successor to Intel’s 670p SSD, the company’s second-generation QLC-based SSD. And based on that description alone, a third generation QLC drive from Soldigm is something that few AnandTech readers would find remarkable. QLC makes for cheap high(ish) capacity SSDs, which OEMs love, while computing enthusiasts are decidedly less enthusiastic about them.

But then the P41 Plus isn’t just a traditional QLC drive.

One of the more interesting ventures out of Intel’s time as a client SSD manufacturer was the company’s forays into cache tiering. Whether it was using flash memory as a hard drive cache, using 3D XPoint as a hard drive cache, or even using 3D XPoint as a flash memory cache, Intel tried several ways to speed up the performance of slower storage devices in a cost-effective manner. And while Intel’s specific solutions never really caught on, Intel’s core belief that some kind of caching is necessary proved correct, as all modern TLC and QLC SSDs come with pseudo-SLC caches for improved burst write performance.

While they are divorced from Intel these days, Solidigm is picking up right where Intel left off, continuing to experiment with cache tiering. Coming from the same group that developed Intel’s mixed 3D XPoint/QLC drives such as the Optane Memory H20, Solidigm no longer has access to Intel’s 3D XPoint memory (and soon, neither will Intel). But they do have access to flash memory. So for their first solo consumer drive as a stand-alone subsidiary, Solidigm is taking a fresh stab at cache tiering, expanding the role of the pSLC cache to serve as both a write cache and a read cache.

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Compute Express Link (CXL) 3.0 Announced: Doubled Speeds and Flexible Fabrics

While it’s technically still the new kid on the block, the Compute Express Link (CXL) standard for host-to-device connectivity has quickly taken hold in the server market. Designed to offer a rich I/O feature set built on top of the existing PCI-Express standards – most notably cache-coherency between devices – CXL is being prepared for use in everything from better connecting CPUs to accelerators in servers, to being able to attach DRAM and non-volatile storage over what’s physically still a PCIe interface. It’s an ambitious and yet widely-backed roadmap that in three short years has made CXL the de facto advanced device interconnect standard, leading to rivals standards Gen-Z, CCIX, and as of yesterday, OpenCAPI, all dropping out of the race.

And while the CXL Consortium is taking a quick victory lap this week after winning the interconnect wars, there is much more work to be done by the consortium and its members. On the product front the first x86 CPUs with CXL are just barely shipping – largely depending on what you want to call the limbo state that Intel’s Sapphire Ridge chips are in – and on the functionality front, device vendors are asking for more bandwidth and more features than were in the original 1.x releases of CXL. Winning the interconnect wars makes CXL the king of interconnects, but in the process, it means that CXL needs to be able to address some of the more complex use cases that rival standards were being designed for.

To that end, at Flash Memory Summit 2022 this week, the CXL Consortium is at the show to announce the next full version of the CXL standard, CXL 3.0. Following up on the 2.0 standard, which was released at the tail-end of 2020 and introduced features such as memory pooling and CXL switches, CXL 3.0 focuses on major improvements in a couple of critical areas for the interconnect. The first of which is the physical side, where is CXL doubling its per-lane throughput to 64 GT/second. Meanwhile, on the logical side of matters, CXL 3.0 is greatly expanding the logical capabilities of the standard, allowing for complex connection topologies and fabrics, as well as more flexible memory sharing and memory access modes within a group of CXL devices.

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Phison and Seagate Announce X1 SSD Platform: U.3 PCIe 4.0 x4 with 128L eTLC

Phison and Seagate have been collaborating on SSDs since 2017 in the client as well as SMB/SME space. In April 2022, they had announced a partnership to develop and distribute enterprise NVMe SSDs. At the Flash Memory Summit this week, the results of the collaboration are being announced in the form of the X1 SSD platform – an U.3 PCIe 4.0 x4 NVMe SSD that is backwards compatible with U.2 slots.

The X1 SSD utilizes a new Phison controller exclusive to Seagate – the E20. It integrates two ARM Cortex-R5 cores along with multiple co-processors that accelerate SSD management tasks. Phison is touting the improvement in random read IOPS (claims of up to 30% faster that the competition in its class) as a key driver for its fit in AI training and application servers servicing thousands of clients. The key specifications of the X1 SSD platform are summarized in the table below. The performance numbers quoted are for the 1DWPD 3.84TB model.

Seagate / Phison X1 SSD Platform
Capacities
1.92 TB, 3.84 TB, 7.68 TB, 15.36 TB (1DWPD models)
1.6 TB, 3.2 TB, 6.4 TB, 12.8 TB (3DWPD models)
Host Interface
PCIe 4.0 x4 (NVMe 1.4)
Form Factor
U.3 (15mm / 7mm z-height)
NAND
128L 3D eTLC
Sequential Accesses Performance
7400 MBps (Reads)
7200 MBps (Writes)
Random Accesses Performance
1.75M IOPS & 84us Latency @ QD1 (4K Reads)
470K IOPS & 10us Latency @ QD1 (4K Writes)
Uncorrectable Bit-Error Rate
1 in 1018
Power Consumption
13.5W (Random Reads)
17.9W (Random Writes)
6.5W (Idle)

Seagate equips the X1 with eTLC (enterprise TLC), power-loss protection capacitors, and includes end-to-end data path protection. SECDED (single error correction / double error detection) and periodic memory scrubbing is done for the internal DRAM as part of the ECC feature. For the contents on the flash itself, the X1 supports the Data Integrity Field / Data Integrity Extension / Protection Information (DIF/DIX/PI) for end-to-end data protection. Various other enterprise-focused features such as SR-IOV support, and NVMe-MI (management interface) are also supported.

Seagate and Phison claim that the X1 SSD can be customized for specific use-cases, and it offers the best performance in class along with the best energy efficiency. In terms of competition in the PCIe 4.0 / U.2 / U.3 space, the X1 goes up against Micron’s 7450 PRO and 7450 MAX (PDF), using their 176L 3D TLC flash, and Kioxia’s CD7-V / CD7-R data center SSDs. On paper, Seagate / Phison’s performance specifications easily surpass those platforms that have been shipping for more than a year now.

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OpenCAPI to Fold into CXL – CXL Set to Become Dominant CPU Interconnect Standard

With the 2022 Flash Memory Summit taking place this week, not only is there a slew of solid-state storage announcements in the pipe over the coming days, but the show is also increasingly a popular venue for discussing I/O and interconnect developments as well. Kicking things off on that front, this afternoon the OpenCAPI and CXL consortiums are issuing a joint announcement that the two groups will be joining forces, with the OpenCAPI standard and the consortium’s assets being transferred to the CXL consortium. With this integration, CXL is set to become the dominant CPU-to-device interconnect standard, as virtually all major manufacturers are now backing the standard, and competing standards have bowed out of the race and been absorbed by CXL.

Pre-dating CXL by a few years, OpenCAPI was one of the earlier standards for a cache-coherent CPU interconnect. The standard, backed by AMD, Xilinx, and IBM, among others, was an extension of IBM’s existing Coherent Accelerator Processor Interface (CAPI) technology, opening it up to the rest of the industry and placing its control under an industry consortium. In the last six years, OpenCAPI has seen a modest amount of use, most notably being implemented in IBM’s POWER9 processor family. Like similar CPU-to-device interconnect standards, OpenCAPI was essentially an application extension on top of existing high speed I/O standards, adding things like cache-coherency and faster (lower latency) access modes so that CPUs and accelerators could work together more closely despite their physical disaggregation.

But, as one of several competing standards tackling this problem, OpenCAPI never quite caught fire in the industry. Born from IBM, IBM was its biggest user at a time when IBM’s share in the server space has been on the decline. And even consortium members on the rise, such as AMD, ended up skipping on the technology, leveraging their own Infinity Fabric architecture for AMD server CPU/GPU connectivity, for example. This has left OpenCAPI without a strong champion – and without a sizable userbase to keep things moving forward.

Ultimately, the desire of the wider industry to consolidate behind a single interconnect standard – for the sake of both manufacturers and customers – has brought the interconnect wars to a head. And with Compute Express Link (CXL) quickly becoming the clear winner, the OpenCAPI consortium is becoming the latest interconnect standards body to bow out and become absorbed by CXL.

Under the terms of the proposed deal – pending approval by the necessary parties – the OpenCAPI consortium’s assets and standards will be transferred to the CXL consortium. This would include all of the relevant technology from OpenCAPI, as well as the group’s lesser-known Open Memory Interface (OMI) standard, which allowed for attaching DRAM to a system over OpenCAPI’s physical bus. In essence, the CXL consortium would be absorbing OpenCAPI; and while they won’t be continuing its development for obvious reasons, the transfer means that any useful technologies from OpenCAPI could be integrated into future versions of CXL, strengthening the overall ecosystem.

With the sublimation of OpenCAPI into CXL, this leaves the Intel-backed standard as dominant interconnect standard – and the de facto standard for the industry going forward. The competing Gen-Z standard was similarly absorbed into CXL earlier this year, and the CCIX standard has been left behind, with its major backers joining the CXL consortium in recent years. So even with the first CXL-enabled CPUs not shipping quite yet, at this point CXL has cleared the neighborhood, as it were, becoming the sole remaining server CPU interconnect standard for everything from accelerator I/O (CXL.io) to memory expansion over the PCIe bus.

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Akasa AK-ENU3M2-07 USB 3.2 Gen 2×2 SSD Enclosure Review: 20Gbps with Excellent Thermals

Storage bridges have become an ubiquitous part of today’s computing ecosystems. The bridges may be external or internal, with the former ones enabling a range of direct-attached storage (DAS) units. These may range from thumb drives using an UFD controller to full-blown RAID towers carrying Infiniband and Thunderbolt links. From a bus-powered DAS viewpoint, Thunderbolt has been restricted to premium devices, but the variants of USB 3.2 have emerged as mass-market high-performance alternatives. USB 3.2 Gen 2×2 enables the highest performance class (up to 20 Gbps) in USB devices without resorting to PCIe tunneling. The key challenges for enclosures and portable SSDs supporting 20Gbps speeds include handling power consumption and managing thermals. Today’s review takes a look at the relevant performance characteristics of Akasa’s AK-ENU3M2-07 – a USB 3.2 Gen 2×2 enclosure for M.2 NVMe SSDs.

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The Intel Core i9-12900KS Review: The Best of Intel’s Alder Lake, and the Hottest

As far as top-tier CPU SKUs go, Intel’s Core i9-12900KS processor sits in noticeably sharp In contrast to the launch of AMD’s Ryzen 7 5800X3D processor with 96 MB of 3D V-Cache. Whereas AMD’s over-the-top chip was positioned as the world’s fastest gaming processor, for their fastest chip, Intel has kept their focus on trying to beat the competition across the board and across every workload.

As the final 12th Generation Core (Alder Lake) desktop offering from Intel, the Core i9-12900KS is unambiguously designed to be the powerful one. It’s a “special edition” processor, meaning that it’s low-volume, high-priced chip aimed at customers who need or want the fastest thing possible, damn the price or the power consumption.

It’s a strategy that Intel has employed a couple of times now – most notably with the Coffee Lake-generation i9-9900KS – and which has been relatively successful for Intel. And to be sure, the market for such a top-end chip is rather small, but the overall mindshare impact of having the fastest chip on the market is huge. So, with Intel looking to put some distance between itself and AMD’s successful Ryzen 5000 family of chips, Intel has put together what is meant to be the final (and fastest) word in Alder Lake CPU performance, shipping a chip with peak (turbo) clockspeeds ramped up to 5.5GHz for its all-important performance cores.

For today’s review we’re putting Alder Lake’s fastest to the test, both against Intel’s other chips and AMD’s flagships. Does this clockspeed-boosted 12900K stand out from the crowd? And are the tradeoffs involved in hitting 5.5GHz worth it for what Intel is positioning as the fastest processor in the world? Let’s find out.

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Intel To Wind Down Optane Memory Business – 3D XPoint Storage Tech Reaches Its End

It appears that the end may be in sight for Intel’s beleaguered Optane memory business. Tucked inside a brutal Q2’2022 earnings release for the company (more on that a bit later today) is a very curious statement in a section talking about non-GAAP adjustments: In Q2 2022, we initiated the winding down of our Intel Optane memory business.  As well, Intel’s earnings report also notes that the company is taking a $559 Million “Optane inventory impairment” charge this quarter.

Beyond those two items, there is no further information about Optane inside Intel’s earnings release or their associated presentation deck. We have reached out to company representatives seeking more information, and are waiting for a response.

Taking these items at face value, then, it would seem that Intel is preparing to shut down its Optane memory business and development of associated 3D XPoint technology. To be sure, there is a high degree of nuance here around the Optane name and product lines here – which is why we’re looking for clarification from Intel – as Intel has several Optane products, including “Optane memory” “Optane persistent memory” and “Optane SSDs”. None the less, within Intel’s previous earnings releases and other financial documents, the complete Optane business unit has traditionally been referred to as their “Optane memory business,” so it would appear that Intel is indeed winding down the Optane business unit, and not just the Optane Memory product.

Intel, in turn, used 3D XPoint as the basis of two product lineups. For its datacenter customers, it offered Optane Persistent Memory, which packaged 3D XPoint into DIMMs as a partial replacement for traditional DRAMs. Optane DIMMs offered greater bit density than DRAM, and combined with its persistent, non-volatile nature made for an interesting offering for systems that needed massive working memory sets and could benefit from its non-volatile nature, such as database servers. Meanwhile Intel also used 3D XPoint as the basis of several storage products, including high-performance SSDs for the server and client market, and as a smaller high-speed cache for use with slower NAND SSDs.

3D XPoint’s unique attributes have also been a challenge for Intel since the technology launched, however. Despite being designed for scalability via layer stacking, 3D XPoint manufacturing costs have continued to be higher than NAND on a per-bit basis, making the tech significantly more expensive than even higher-performance SSDs. Meanwhile Optane DIMMs, while filling a unique niche, were equally as expensive and offered slower transfer rates than DRAM. So, despite Intel’s efforts to offer a product that could crossover the two product spaces, for workloads that don’t benefit from the technology’s unique abilities, 3D XPoint ended up being neither as good as DRAM or NAND in their respective tasks – making Optane products a hard sell.

As a result, Intel has been losing money on its Optane business for most (if not all) of its lifetime, including hundreds of millions of dollars in 2020. Intel does not break out Optane revenue information on a regular basis, but on the one-off occasions where they have published those numbers, they have been well in the red on an operating income basis. As well, reports from Blocks & Files have claimed that Intel is sitting on a significant oversupply of 3D XPoint chips – on the order of two years’ of inventory as of earlier this year. All of which underscores the difficulty Intel has encountered in selling Optane products, and adding to the cost of a write-down/write-off, which Intel is doing today with their $559M Optane impairment charge.

This is breaking news and will be updated with additional information as it becomes available

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Silicon Motion Announces SM8366 PCIe 5.0 x4 NVMe Controller and MonTitan SSD Solutions Platform for Enterprise Storage

In the lead up to the Flash Memory Summit next week, many vendors have started announcing their new products. Today, Silicon Motion is unveiling their first enterprise-focused PCIe 5.0 NVMe SSD controllers set. These controllers find themselves embedded in a flexible turnkey solutions platform encompassing different EDSFF standards. A follow-up to the SM8266 introduced in November 2020, the SM8366 and SM8308 belong to Silicon Motion’s 3rd Generation enterprise NVMe controller family.

Silicon Motion’s 3rd Generation Enterprise SSD Controllers
 
SM8366
SM8308
Host Interface
PCIe 5.0 x4 / x2 (dual-port x2+x2 or x1+x1 capable)
NAND Interface
16ch, 2400 MT/s
8ch, 2400 MT/s
DRAM
2x 40-bit DDR4-3200 / DDR5-4800
(32-bit data + 8-bit ECC per channel)
Max. SSD Capacity
128 TB
Sequential Read
14 GB/s
Sequential Write
14 GB/s
Random Read
3 M IOPS
Random Write
2.8 M IOPS
Namespaces
Up to 128, with a total of 1024 queue pairs

Hyperscalers / cloud vendors require turnkey reference designs to quickly evaluate the capabilities of new controllers. In enterprise applications, the controller hardware is only half the story. The associated firmware / SDK, and user-programmability to enable customer differentiation are also key aspects. Keeping this in mind, Silicon Motion is also putting focus on the SM8366 reference design by giving it a separate moniker – MonTitan.

The MonTitan platform refers to the turnkey design / firmware development platform based on the OCP Data Center NVMe SSD and NVMe 2.0 specifications. Hyperscalers can readily deploy the MonTitan platform into their infrastructure for evaluation, while datacenter SSD vendors can use it to make and market their own datacenter and enterprise SSDs. The platform is currently available in U.2, E1.S, and E3.S form-factors.

Silicon Motion claims that the platform’s ASIC and firmware combination architecture allows enabling of enterprise-level security without compromising on performance and QoS. Towards this, they are touting two key features – PerformaShape and NANDCommand.

NVMe SSD controllers can present the SSD as multiple distinct storage volumes each with its own I/O queue to the host system (namespaces). The PerformaShape algorithm can optimize the SSD performance differently for each namespace using per-namespace user-defined QoS settings. Silicon Motion claims true hardware isolation in this case to deliver maximum bandwidth while ensuring that latency, QoS, and power targets are met / obeyed. The NANDCommand feature refers to Silicon Motion’s use of real-time machine learning along with the LDPC engine to help with endurance (paritcularly important for QLC).

The claimed performance numbers for the SM8366 controller can vary for specific designs depending on the NAND technology, number of dice, and form-factor power limitations. The company indicated that specific numbers for different form-factor reference designs will be announced later. Sampling is slated to begin in Q4 2022.

Silicon Motion’s press release shows the usual suspects providing supporting quotes – Micron, KIOXIA, and YMTC from amongst the NAND suppliers. Alibaba Cloud has also expressed interest in evaluating the platform, which bodes well for Silicon Motion’s enterprise SSD controller efforts.

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